The escalating requirements for increased densification and performance in ultra-large scale integration semiconductor wiring require responsive changes in interconnection technology. High density demands for ultra-large scale integration semiconductor wiring require planarized conductive patterns comprising conductive lines and/or interwire spacings of less than 0.35 microns.
A traditional method for forming interconnection structures comprises the use of a subtractive etching or etch back step as the primary metal patterning technique. Such a traditional method involves the formation of a dielectric layer on a semiconductor substrate, typically monocrystalline silicon, with conductive contacts/vias formed in the insulating layer. A metal layer, such as tungsten, aluminum, or alloys thereof, is deposited on the insulating layer, and a photoresist mask is formed on the metal layer having a pattern corresponding to the desired conductive pattern. The metal layer is then etched through the photoresist mask to form the conductive pattern. A dielectric layer is then applied to the resulting conductive pattern filling in the interwiring spaces between the conductive lines.
There are various problems attendant upon the traditional etch back technique. For example, it is difficult to form an adequately planarized layer subsequent to filling in the interwiring spacings between the conductive lines, as by conventional etching and chemical-mechanical polishing (CMP) planarization techniques, particularly with reducer interwiring spacings. In addition, the traditional etch back technique often results in the generation of voids in the filled-in interwiring spacings. Additional difficulties include trapping of impurities of volatile materials in the interwiring spacings thereby exposing the semiconductor device to potential damage. Moreover, it is difficult to provide adequate step courage using the traditional etch back technique.
Prior attempts to overcome the disadvantages of the traditional etch back technique involve the application of damascene to form a conductive pattern. Damascene is an art which has been employed for centuries in the fabrication of jewelry, and has recently been adapted for application in the semiconductor industry. Damascene basically involves the formation of a trench which is filled with a metal. Thus, damascene differs from the traditional etch back techniques of providing an interconnection structure by forming a pattern of trenches in a dielectric layer, which trenches are filled in with metal to form the conductive pattern followed by planarization vis-a-vis the traditional etch back technique of depositing a metal layer, forming a conductive pattern with interwiring spacings, and filling in the interwiring spacings with dielectric material.
In co-pending application Ser. No. 08/320,516 filed on Oct. 11, 1994, prior art single and dual damascene techniques are disclosed, in addition to several improved dual damascene techniques for greater accuracy in forming fine line patterns with minimal interwiring spacings. However, there exists a need for a simplified method of accurately forming interconnection structures with minimal dimensions, e.g., as small as about 0.15 microns for vias and trenches.